Engineering Change Order (ECO)-engineerror怎么解决apex

A semiconductor chip undergoes synthesis, placement, clock tree synthesis and routing processes before going for fabrication. All these processes require some time, hence, it requires time (9 months to 1 year for a normal sized chip) for a new chip to be sent for fabrication. As a result of cut-throat competition, all the semiconductor companies stress on Cycle-time reduction to be ahead of others in the race. New ways are being found out to achieve the same. New techniques are being developed and more advanced tools are being used. Sometimes, the new chip to be produced may be an incremental change over an existing product. In such a case, there may not be the need to go over the same cycle of complete synthesis, placement and routing. However, everything may be carried out in incremental manner so as to reduce engineering costs, time and manufacture costs.

It is a known fact that the fabrication process of a VLSI chip involves manufacture of a number of masks, each mask corresponding to one layer. There are two kinds of layers – base and metal. Base layers contain the information regarding the geometry and kind of transistors, resistors, capacitors and other devices. Metal layers contain information regarding metal interconnects used for connection of devices. For a sub-micron technology, the mask costs may be greater than a million dollars. Hence, to minimize the cost, the tendency is to reuse as many masks as possible. So, it is tried to implement the ECO with minimal number of layers change. Also, due to cycle time crunch, it is a tradition to send the base layers for the manufacture of masks while the metals are still modified to eliminate any kind of DRC’s. This saves around two weeks in cycle time. The base layer masks are developed while metal layers are still being modified.

What conditions cause an Engineering Change Order: As mentioned above, ECO are needed when the process steps are needed to be executed in an incremental manner. This may be due to-

Some  functionality enhancement of the existing device. This functionality enhancement change may be too small to undergo all the process steps again

There may be some design bug that needs to be fixed and was caught very late in     the design cycle. It is very costly to re-run all the process cycle steps for each bug in terms of time and cost. Hence, these changes need to be taken incrementally.

Normally, there is a case that design enhancements/functional bug fixes are being implemented after the design has already been sent for fabrication. For instance, the functional bug may be caught in silicon itself.  To fix the bug, it is not practical to restart the cycle.

The ECO process starts with the changes in the definition to be implemented into the RTL. The resulting netlist synthesized from the modified netlist is, then, compared with the golden netlist being implemented. The logic causing the difference is then implemented into the main netlist. The netlist, then, undergoes placement of the incremental logic, clock tree modifications and routing optimizations based upon the requirements.

Kinds of ECO: The engineering change orders can be classified into two categories:

All layers ECO: In this, the design change is implemented using all layers. This kind of ECO provides advantage in terms     of cycle time and engineering costs. It is implemented whenever the change     is not possible to be carried out without all layer change e.g. there is     an updation in a hard macro cell or the change may require updation of 100’s of cells. It is almost impossible to contain such a large change to a few layers only.

Metal-only ECO: As discussed above, due to incurring  costs, sometimes, it may not be practical to use all the layers (base + metal) to do the ECO. In that case, to minimize the cost, it is required     to be completed with changes only in minimal number of metal layers. These     days, it is expected that every design will be re-opened for the ECOs. So, an adequate number of spare cells are sprinkled during the implementation  all over the design to be used later on. These cells are spread uniformly over the design. The inputs of these cells are tied. Whenever the need for an ECO arises, the cells to be implemented can be mapped into the existing spare cells. Hence, there is no need to change the base layers in such a case. Only the connections need to be updated which can be done by changing the metal layers only. Hence, the base layer cost is saved.

Steps to carry out an ECO: The ECOs are best implemented manually. There exist some automated ways to carry out the functional ECOs, but the most efficient and effective method is to implement manually. Generally, following steps are employed to carry out Engineering Change Orders:

The RTL with ECO implemented is synthesized and compared with the golden netlist.

The delta is implemented into the golden netlist. The modified netlist is then again      compared with the synthesized netlist to ensure the logic has been      implemented correctly.

The logic is the placed incrementally. However, if it is metal-only ECO, spare cells in      the proximity of the changed logic are found out.

The connections are, then, modified in metal layers.

Metal ECO – the process

A metal-only ECO is carried out by changing only metal interconnects in the design. Metal-only ECOs are very common in today’s semiconductor industry as they save complete silicon re-spin. Sometimes there may be need to change the design for various reasons, and that too, a minor change. These changes may be due to some bug in the design or due to customer demand. A metal-only ECO enables the design to be re-fabricated only for a few layers. It is very cost-effective as for complete silicon re-spin, there may be a requirement of around 100 layer masks to be manufactured. Metal-only ECOs enable the older masks to be used for most of the layers. Only the layers with changes in them need to be manufactured again, which is usually 2 to 4 in case of metal-only ECOs.

The steps to carry out metal-only ECOs are explained below:

1.) A number of spare cells are sprinkled throughout the design before being taped-out so as to facilitate metal layer ECOs later on. The set of spare cells is chosen very carefully considering in mind the nature of design and the probability of metal ECO later on (it depends upon how mature the design building blocks are)

2.)  First, the changes to be made are evaluated if these can be carried out by changing only metal layers. For this purpose, spare cells in the vicinity of the ECO location need to be observed. If there is enough number of spare cells there, these can be used. On the other hand, if there is not enough number of spare cells to represent the logic change, the ECO cannot be carried out using only metal layers. It has to be, then, carried out using all the layers as more cells will need to be added. It will, then, result in re-spin of the design. 

3.) If there is enough number of spare cells available, the appropriate spare cells to represent the design change are selected in the vicinity of the logic to be changed. Interconnects are, then, modified so as to represent the modified circuit. 

4.) The resulting layout is checked for timing and DRC/LVS violations. If everything is fine, the design is sent to be fabricated. There, masks for the modified layers are manufactured using the older masks for layers not modified.

Spare Cells

We have discussed in our post titled Engineering Change Order about the important to have a uniform distribution of spare cells in the design. Nowadays, there is a trend among the VLSI corporations to implement metal-only functional and timing ECOs due to their low-cost. Let us discuss about the spare cells in a bit more detail here.

Figure showing spare cells in the design

Kinds of spare cells: There are many variants of spare cells in the design. Designs are full of spare inverters, buffers, nand, nor and specially designed configurable spare cells. However, based on the origin of spare cells, these can be divided into two broad categories:Spare cells are put onto the chip during implementation keeping into view the possibility of modifications that are planned to be carried out into the design without disturbing the layers of base. This is because carrying out design changes with minimal layer changes saves a lot of cost from fabrication point of view as each layer mask has a significant cost of its own. Let us start by defining what a spare cell is. A spare cell can be thought of as a redundant cell that is not used currently in the design. It may be in use later on, but currently, it is sitting without doing any job. A spare cell does not contribute to the functionality of the device. We can compare a spare cell with a spare wheel being carried in a motor car to be used in case one of the wheels gets punctured. In that case, the spare wheel will be replacing the main wheel. Similarly, a spare cell can be used to replace an existing cell if the situation demands (eg. to meet the timing). However, unlike spare wheels, spare cells may be added to the design even if they do not replace any existing cell according as the need arises.

Those used deliberately as spare cells in the design: As discussed earlier, most of the designs today have spare cells sprinkled uniformly. These cells have inputs and outputs tied to either ‘0’ or ‘1’ so that they contribute minimum to static and dynamic power.

Those converted into spare cells due to design changes: There may be a case that a cell that is being identified as a spare now was a main cell in the past. Due to some design changes, the cell might have been replaced by another cell. Also, some cells have floating outputs. These can be used as spare cells. We can also use the used buffers as spare cells if removing the buffer does not introduce any setup/hold violation in the design.

Advantages of using spare cells in the design: Introduction of spare cells into the design offers several advantages such as:

Reusability: A design change can be carried out using metal layers only. So, the base layers can be re-used for fabrication of new chips.

Cost reduction: Significant amount of money is saved both in terms of engineering and manufacture costs.

Design flexibility: As there are spare cells, small changes can be taken into the design without much difficulty. Hence, the presence of spare cells provides flexibility to the design.

Cycle time reduction: Nowadays, there is a trend to tape out base layers to the foundry for fabrication as masks are not prepared in parallel. In the meantime, the timing violations/design changes are being carried out in metal layers. Hence, there is cycle time reduction of one to two weeks.

Disadvantages of using spare cells: In addition to many advantages, usage of spare cells offers some disadvantages too. These are:

Contribution to static power: Each spare cell has its static power dissipation. Hence, greater amount of spare cells contribute more to power. But, in general, this amount of power is insignificant in comparison to total power. Spare cells should be added keeping into consideration their contribution to power.

Area: Spare cells occupy area on the chip. So, more spare cells mean more density of cells.

Thus, we have discussed about the spare cells here. Spare cells are used almost in every design in each device manufactured today. It is important to make an intelligent selection of spare cells to be sprinkled in the design. Many technical papers have been published stating its importance and on the structure of the spare cells that can be generalized to be used as any of the logic gate. In general, a collection of nand/nor/inverters/buffers is sprinkled more or less uniformly. The modules where more number of ECOs are expected, (like a new architecture being used for the first time) should be sprinkled with more spare cells. On the contrary, those having stable architectures are usually sprinkled with less number of spare cells as the probability of an ECO is very less in the vicinity of these modules/macros.

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